The present invention generally relates to a semiconductor memory device, and more specifically, a fuse that is blown by a laser irradiated in a repair process.
If at least one memory cell of a semiconductor device has a defect in the manufacturing of the semiconductor device, the device does not serve as a memory, so that the device is regarded as being defective. However, although there is a defect in one memory cell of the memory, the device is discarded, thereby decreasing the device yield.
Currently, a defective cell is repaired with a redundancy cell which is formed in a memory device during the manufacturing process, thereby repairing the device to improve the yield.
When the defective memory cell is found through a test in a wafer state, a program to replace an address of the corresponding cell with an address signal of the redundancy cell is performed in an internal circuit. Of these programs, a widely used method is to cut a fuse using a laser beam. A wire disconnected by laser irradiation is referred to as a fuse, and the disconnected site and its surrounding region are referred to as a fuse box.
FIG. 1 is a plane diagram illustrating a fuse circuit unit of a conventional semiconductor device.
Referring to FIG. 1, fuses F1˜F4 are arranged in a straight line penetrating a fuse box region 10. A metal line 20 and a contact 30 connecting the metal line 20 to each of the fuses F1˜F4 are formed in both terminals of each of the fuses F1˜F4. The fuses F1˜F4 are formed in a single layer using a metal line or a plate electrode of a previously formed capacitor. The reference number 40 represents a blowing region where the fuse is cut by a laser beam irradiated during a repair process.
FIG. 2 is a circuit diagram illustrating the fuse circuit unit of FIG. 1.
The fuse circuit includes a plurality of fuses F1˜F4 connected in parallel. One side of each of the fuses F1˜F4 is connected in common to a node B so as to receive power voltage VDD through a transistor PT. The other side of each of the fuses F1˜F4 are connected to repair transistors N1˜N4, respectively. The repair transistors N1˜N4 have each gate to receive address signals A<0>˜A<3> so that the other side of each of the fuses F1˜F4 may be connected to a ground voltage VSS through the transistor NT in response to the address signals A<0>˜A<3>.
However, although the size of the fuse and a space between the fuses become narrower due to high integration of the semiconductor device, there is a limit to the reduction of the size of the fuse and the space between the fuses in order to blow a fuse.
While the area occupied by other circuits of the semiconductor device is reduced, a region where the fuse circuit region is formed is not decreased. As a result, the fuse region occupies a relatively larger area in the semiconductor memory device. When the fuse region occupies a large area, there is a limit in reduction of the size of the semiconductor memory device, which inhibits increase of the net number of die.